Method of fabrication of metal oxide semiconductor field effect transistor

ABSTRACT

A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of an application Ser. No.11/308,718, filed on Apr. 26, 2006, now pending. The entirety of theabove-mentioned patent applications is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention is related to a semiconductor device and itsmethod of fabrication, especially is related to a method of fabricationof a metal oxide semiconductor field effect transistor having strainedlayer.

2. Description of Related Art

The semiconductor industry and wafer fabrication is headed towardshigher efficiency and ultra large-scale integration. For the sake ofaccomplishing higher effectiveness using the same amount of footprintarea, the wafer characteristic dimensions and supply voltage willcontinue to diminish Generally speaking, if other characteristics areheld constant, the power consumption of each device will increaseaccording to the on/off frequency. Therefore, although the supplyvoltage and the capacitance load are decreased, the power consumption ofthe wafer is gradually increasing. Furthermore, when the dimensions ofthe field effect transistor have become smaller, the commonly knownshort channel effect will become more pronounced, thus contributing tothe severity of the power consumption issue.

The method for improving short channel effect includes the dispositionof the source and the shallow source/drain extensions. Using fabricationof the metal oxide semiconductor field effect transistor as an example,an implantation of ions is performed within an elongated region of highdosage first through a mask after the gate is established, and at thetwo side walls of the channel to form shallow extensions. Later, aspacer is formed at the side wall of the gate, and a source/drain layeris formed in the substrate outside of the spacer. Followed by anannealing procedure is later performed. Annealing to activate the dopingion is then performed, and the shallow extending internally dopant isallowed to diffuse towards the channel region. Although the dopantdiffused towards the channel region can improve, for example, punchthrough and other issues, the dopant diffusion rate is difficult tocontrol, and excessive dopant will damage the transistor efficiency.

Furthermore, for improving further on the short channel effect,conventional technology is using halo implant to inhibit the so-calledpunch through effect. However, the ion for the halo implant willdecrease the drain current, and based on the fact of continuous gatedimensional shrinkage, this issue will become more pronounced, thusdisallowing the transistor efficiency to further improve.

SUMMARY OF THE INVENTION

The present invention is directed to a metal oxide semiconductor fieldeffect transistor, for raising the drain current.

In one embodiment, a metal oxide semiconductor field effect transistorincludes a substrate, a gate structure disposed on the substrate, aspacer disposed on a side wall of the gate structure; and a source/drainstructure. The source/drain structure includes a source/drain extensionlayer disposed in the substrate and below the spacer, a source/drainlayer disposed in the substrate and outside of the spacer, and a dopantdiffusion barrier layer disposed directly under the source/drainextension layer. The depth of the source/drain layer is larger than thedepth of the source/drain extension layer. An entire of the source/drainstructure is comprised of a strained material comprising two differentatoms.

In one embodiment, a metal oxide semiconductor field effect transistorincludes a substrate, a gate structure disposed on the substrate, aspacer disposed on a side wall of the gate structure, a source/drainextension layer disposed in the substrate and below the spacer, asource/drain layer disposed in the substrate and outside of the spacer,and a dopant diffusion barrier layer disposed directly under thesource/drain extension layer. The depth of the source/drain layer islarger than the depth of the source/drain extension layer; and an entireof the source/drain extension layer and the dopant diffusion barrierlayer are comprised of a strained material comprising two differentatoms.

In one embodiment, a metal oxide semiconductor field effect transistorincludes a substrate, a gate structure disposed on the substrate, aspacer disposed on a side wall of the gate structure, a source/drainextension layer disposed in the substrate and below the spacer, asource/drain layer disposed in the substrate and outside of the spacer,and a dopant diffusion barrier layer, disposed directly under thesource/drain extension layer. The depth of the source/drain layer islarger than the depth of the source/drain extension layer; and a topsurface of the source/drain extension layer is higher than a top surfaceof the substrate.

To better understand the aforementioned advantages, characteristics, andfunctionalities, further aspects of the present invention, and furtherfeatures and benefits thereof, are described below. The accompanyingdrawings, which are incorporated herein and form a part of thespecification, illustrate the present invention and, together with thedescription, further server to explain the principles of the inventionand to enable a person skilled in the pertinent art to make and use theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A to FIG. 1G are a plurality of cross-sectional views illustratingthe fabrication process of a metal oxide semiconductor field effecttransistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the metal oxide semiconductor fieldeffect transistor, according to another embodiment of the presentinvention.

FIG. 3A to FIG. 3G are a plurality of cross-sectional views illustratingthe fabrication process of the metal oxide semiconductor field effecttransistor according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of the metal oxide semiconductor fieldeffect transistor, according to another embodiment of the presentinvention.

DESCRIPTION OF THE EMBODIMENTS First Embodiment

FIG. 1A to FIG. 1G are a plurality of cross-sectional views illustratingthe fabrication process of the metal oxide semiconductor field effecttransistor according to an embodiment of the present invention. In afirst embodiment, the metal oxide semiconductor field effect transistorof the present invention is illustrated using a PMOS process as anexample.

Referring to FIG. 1A, a substrate 100 is first provided, where thesubstrate 100, for example, is a silicon-based substrate, a pure siliconsubstrate, a silicon on insulator (SOI) substrate, a germanium channelsubstrate, a substrate having bulk strain, or a substrate havingcrystallographic orientation. A plurality of isolation structures 102are formed in the substrate 100. The material of the isolation structure102, for example, is silicon oxide. A gate structure 104 is formed onthe substrate 100 between the isolation structures 102. The gatestructure 104 at least includes a gate dielectric layer 104 a, a gate104 b, a spacer 104 c and a gate protection layer 104 d. The material ofthe gate dielectric layer 104 a, for example, is silicon oxide, thematerial of the gate 104 b, for example, is doped polysilicon, thematerial of the spacer 104 c, for example, is silicon oxide, and thematerial of the gate protection layer 104 d, for example, is siliconnitride or silicon oxide. Furthermore, a channel region 106 of the metaloxide semiconductor field effect transistors is formed at the substrate100 and below the gate structure 104.

Later, referring to FIG. 1B, a dry etching process 108 is performed, aportion of the substrate 100 is removed, and a recess 110 is formed atthe two side walls of the gate structure 104 in the substrate 100. Thedry etching process 108, for example, is reactive ion etching(RIE). Areaction gas used in the dry etching process 108, for example, ishexafluroethane (C₂F₆) or helium.

Later, referring to FIG. 1C, a source/drain extension layer 112 isformed inside the recess 110. The material of the source/drain extensionlayer 112, for example, is silicon germanium. The composite structure ofthe silicon germanium is typically represented by SiXGe_(1-x), or SiGecan be directly used for representation, wherein x is from 0 to 1.Furthermore, the structure of the source/drain extension layer 112, forexample, includes epitaxy. The method of fabrication of the source/drainextension layer 112, for example, is selective epitaxial deposition,which allows silicon germanium to grow only on the silicon, and not onthe silicon oxide or the silicon nitride. In other words, silicongermanium only grows in the recess 110, and not on the spacer 104 c, thegate protection layer 104 d, and the isolation structure 102. Theselective epitaxial deposition, for example, is vapor phase epitaxy,which includes reduced pressure chemical vapor deposition epitaxialdeposition, atmospheric pressure chemical vapor deposition epitaxy, andultra high vacuum chemical vapor deposition epitaxy.

A point worthy to mention is that, because the lattice constant ofgermanium is larger than silicon, therefore, the source/drain extensionlayer 112 consists of the silicon germanium is a strained layer. Inother words, due to the inner stress, the silicon germanium lattice ofthe source/drain extension layer 112, produce an anisotropic structure,and thus changing the conduction band and the valence band. Because thesource/drain extension layer 112 is bonded to the substrate 100, theconduction band and the valence band can be tailored to perform designdiscontinuously to produce quantum well and built-in electric field,therefore, the rate of penetration of the carrier of the interfacebetween the source/drain extension layer 112 and the substrate 100 isallowed to be increased. In summary, the source/drain extension layer112, by employing silicon germanium as material, can improve theefficiency of the metal oxide semiconductor field effect transistor.

Furthermore, the source/drain extension layer 112, for example, includesP-type dopants. The P-type dopants, for example, are intended to performin-situ doping injection and ex-situ doping during the forming of thesource/drain extension layer 112. In comparison, in-situ doping allowsthe source/drain extension layer 112 to have higher active dopantconcentration. Furthermore, because the source/drain extension layer 112is a strained layer which uses silicon germanium as material, therefore,the source/drain extension layer 112 will exert a stress on the channelregion 106. This stress and the aforementioned highly-activated dopantconcentration will increase the saturation-region drain current,(Idsat), and the linear-region drain current, (Idlin), of thetransistor. Therefore, the P-type dopant can also, after the forming ofsource/drain extension layer 112, perform ex-situ dopant injection.Furthermore, the P-type dopants, for example, are boron ions. One thingworth mentioning is that, after the forming of the source/drainextension layer 112, the procedure of doped activation annealing istypically performed, and the P-type dopant is allowed to diffuse towardsthe channel region 106 below the gate structure 104. For the sake ofeffectively controlling the diffusion rate of the P-type dopants in thepresent embodiment, prior to the forming of the source/drain extensionlayer 112, a dopant diffusion barrier layer 114 formed inside the recess110 is further included, but the present invention is not only limitedto this. The material of the dopant diffusion barrier layer 114, forexample, is silicon germanium. Furthermore, the dopant diffusion barrierlayer 114, for example, includes N-type dopants, for preventingexcessive P-type dopants from diffusing towards the channel region 106.The method of fabrication of the dopant diffusion barrier layer 114, forexample, is the aforementioned selective epitaxial deposition.Furthermore, in another embodiment, the germanium composition ratio ofthe portion of the source/drain extension layer 112 adjacent to thesubstrate 100, for example, is larger than the germanium compositionratio of the portion of the source/drain extension layer 112 disposed ata farther distance to the substrate 100. This type of design allows theportion of the source/drain extension layer 112 closer to the channelregion 106 to have more germanium atoms for preventing the excessiveP-type dopant from diffusing towards the channel region 106.Furthermore, the germanium composition ratio of the source/drainextension layer 112, for example, is of gradient distribution. As can beseen, when the source/drain extension layer 112 includes P-type dopants,the germanium distribution of the source/drain extension layer 112 canbe used to control the quantity of P-type dopants diffused towards thechannel region 106.

Later, referring to FIG. 1D, a spacer 116 is formed at the two sidewalls of the gate structure 104. The material of the spacer 116, forexample, is silicon nitride, and the method of fabrication of the spacer116 is a conventional technique used and known by those skilled in theart, therefore, no further details are described here.

Later, referring to FIG. 1E, a dielectric layer 118 is formed on theisolation structure 102. The material of the dielectric layer 118, forexample, is silicon oxide or silicon nitride. The method of fabricationof the dielectric layer 118, for example, includes forming a dielectriclayer over all of the structures illustrated in FIG. 1D, then performinga photolithography and etching process to expose the spacer 116 and thesource/drain extension layer 112 thereby forming the dielectric layer118. Later, using the spacer 116 and the dielectric layer 118 as a mask,a dry etching process 120 is performed for removing portions of thesource/drain extension layer 112 and portions of the substrate 100 toform a recess 122. Furthermore, because the metal oxide semiconductorfield effect transistor of the present embodiment further includes thedopant diffusion barrier layer 114, therefore, the dry etching process120 further includes the removal of a portion of the dopant diffusionbarrier layer 114. In addition, reaction gas used in the dry etchingprocess 120 during removal of silicon germanium is, for example, HBr,SF6, or Cl₂.

Later, referring to FIG. 1F, inside the recess 122, a source/drain layer124 is deposited. The material of the source/drain layer 124, forexample, is silicon germanium, and the structure of the source/drainlayer 124, for example, is an epitaxy layer. In addition, because thematerial of the source/drain layer 124 is silicon germanium, therefore,the source/drain layer 124 is a strained layer, thus can improve theefficiency of the metal oxide semiconductor field effect transistor. Themethod of fabrication of the source/drain layer 124, for example, is theaforementioned selective epitaxial deposition, which only allows silicongermanium to grow on the silicon, and not to grow on silicon oxide orsilicon nitride. In other words, silicon germanium will only grow on therecess 122, and will not grow on the gate protection layer 104 d, thespacer 116 and the dielectric layer 118. Furthermore, the source/drainlayer 124, for example, includes P-type dopants. For example, P-typedopants are intended to perform in-situ doping injection during theforming of the source/drain layer 124. In comparison with ex-situdoping, in-situ doping can make the source/drain layer 124 to havehigher activation doping concentration. Furthermore, because thesource/drain layer 124 is a strained layer, using silicon germanium asthe material, the source/drain layer 124 therefore exerts a stress onthe channel region 106. This stress and the aforementioned highactivation doping concentration will increase the saturation-regiondrain current and the linear-region drain current of the transistor.Indeed, after the forming of the source/drain layer 124, ex-situ dopinginjection can also be performed. Furthermore, the P-type dopant of thesource/drain layer 124, for example, is boron ion.

Later, referring to FIG. 1G, the gate protection layer 104 d and thedielectric layer 118 are removed. The method for removing the gateprotection layer 104 d and the dielectric layer 118, for example, is awet etching process, and this wet etching process, for example, uses hotphosphoric acid or hydrofluoric acid as an etchant. Later, a metalsilicide layer 126 is formed on the gate 104 b, on the gate structure102 and also on the source/drain layer 124, for decreasing the contactresistance between the subsequently formed contact and the source/drainlayer 124 and the contact resistance between the contact and the gate104 b. The material of the metal silicide layer 126, for example, isNi(SiGe). The method of fabrication of the metal silicide layer 126, forexample, is first to deposit a layer of nickel, later a rapid thermalanneal(RTA), is performed. The material and method of fabrication of theaforementioned metal silicide layer 126 is an embodiment, however, thepresent invention is not limited to this only. Later, subsequentprocedures are performed to complete the fabrication of the metal oxidesemiconductor field effect transistor.

Because the dopant diffusion barrier layer is formed prior to formingthe source/drain extension layer in the present invention, therefore,after the forming the source/drain extension layer, the P-type dopantsis blocked because of activation annealing when diffuse towards thechannel region. Furthermore, because the germanium composition ratio ofthe portion of the source/drain extension layer 112 adjacent tosubstrate 100, for example, is larger than the germanium compositionratio of the portion of the source/drain extension layer 112 disposed ata farther distance to the substrate 100, therefore, P-type dopants,because of activation annealing, can have controlled diffusing ratetowards the channel region. Because the diffusing rate of the P-typedopants towards the channel region is well controlled, therefore, thefabrication tolerance is increased.

Second Embodiment

FIG. 2 is a cross-sectional view of a metal oxide semiconductor fieldeffect transistor, according to another embodiment of the presentinvention.

Referring to FIG. 2, this metal oxide semiconductor field effecttransistor primarily includes a substrate 200, an isolation structure202, a gate structure 204, a spacer 216, a source/drain extension layer212, and a source/drain layer 224. The substrate 200, for example, is asilicon-based substrate, a silicon on insulator (SOI) substrate, agermanium channel substrate, a substrate having bulk strain, or asubstrate having crystallographic orientation. The gate structure 204 isdisposed on the substrate 200 between the isolation structures 202. Aportion of the substrate 200 below the gate structure 204 is the channelregion of the metal oxide semiconductor field effect transistor. Thespacer 216 is disposed on the side wall of the gate structure 204. Thesource/drain extension layer 212 is disposed in the substrate 200 andunder the spacer 216, and the source/drain layer 224 is disposed in thesubstrate 200 and outside of the spacer 216, and the depth of thesource/drain layer 224 is larger than the depth of the source/drainextension layer 212. The source/drain extension layer 212 and thesource/drain layer 224 are both strained layers. The followingdescriptions serve to illustrate the advantages and structure of the twostrained layers.

The structure of the source/drain extension layer 212, for example, isepitaxy, and the structure of the source/drain layer 224 can also beepitaxy. Furthermore, the material of the source/drain extension layer212, for example, is silicon germanium, and the material of thesource/drain layer 224 can also be silicon germanium. Furthermore,because germanium lattice constant is larger than silicon, therefore,the adopting of silicon germanium as material by the source/drainextension layer 212 and the source/drain layer 224 is a strained layer.The source/drain extension layer 212 and the source/drain layer 224 willexert stress on the channel region 206, thus increasing thesaturation-region drain current and the linear-region drain current ofthe transistor. Furthermore, the source/drain extension layer 212, byadopting silicon germanium as material, can allow the rate ofpenetration of the carrier of the interface between the source/drainextension layer 212 and the substrate 200 to be increased, thusimproving the efficiency of the metal oxide semiconductor field effecttransistor.

Furthermore, the source/drain extension layer 212, for example, includesP-type dopants. This P-type dopants, for example, are boron ions. Thegermanium composition ratio of a portion of the source/drain extensionlayer 212 adjacent to the substrate 200, for example, is larger than thegermanium composition ratio of a portion of the source/drain extensionlayer 212 disposed at a farther distance to the substrate 200. TheP-type dopants, for blocking the source/drain extension layer 212, arethereby diffused towards the channel region 206 because of heat, or atleast control the quantity of P-type dopants diffusing towards thechannel region 206. Furthermore, the germanium composition ratio of thesource/drain extension layer 212, for example, is of gradientdistribution. Furthermore, the metal oxide semiconductor field effecttransistor of the present invention further includes a dopant diffusionbarrier layer 214, disposed between the source/drain extension layer 212and the substrate 200. The material of the dopant diffusion barrierlayer 214, for example, is silicon germanium, and the dopant diffusionbarrier layer 214, for example, includes N-type dopants. Because of theset up of the dopant diffusion barrier layer 214, the P-type dopants canbe further blocked or controlled, are thus diffused towards the channelregion 206, or at least control the quantity of the P-type dopantsdiffused towards the channel region 206. In addition, the source/drainlayer 224 can also include P-type dopants, and these P-type dopants, forexample, are boron ions.

Because the source/drain extension layer and the source/drain layer ofthe metal oxide semiconductor field effect transistor of the presentinvention are of strained layers, therefore, the source/drain extensionlayer and the source/drain layer will exert stress towards the channelregion, thereby increasing the saturation-region drain current and thelinear-region drain current of the transistor. Furthermore, because thematerial of the source/drain extension layer and the source/drain layerare both silicon germanium, therefore, the efficiency of the metal oxidesemiconductor field effect transistor can be increased. In addition,because the dopant diffusion barrier layer is set up and thesource/drain extension layer has a specified distribution method for thegermanium composition ratio, therefore, the diffusion towards thechannel region of the dopant under heating inside the source/drainextension layer can be blocked, or at least the quantity of the dopantsdiffused towards the channel region can be controlled.

Third Embodiment

FIG. 3A to FIG. 3G are cross-sectional views illustrating a fabricationprocess of a metal oxide semiconductor field effect transistor accordingto a third embodiment of the present invention.

In the third embodiment, a NMOS fabrication process is described as anexample for the illustration of the metal oxide semiconductor fieldeffect transistor of the present invention.

Referring to FIG. 3A, first, a substrate 300 is provided. The substrate300, for example, is a silicon-based substrate, a silicon on insulator(SOI) substrate, a germanium channel substrate, a substrate having bulkstrain, or a substrate having crystallographic orientation. A pluralityof isolation structures 302 are formed in the substrate 300. Thematerial of the isolation structure 302, for example, is silicon oxide.A gate structure 304 is formed on the substrate 300 between theisolation structures 302. The gate structure 304 at least includes agate dielectric layer 304 a, a gate 304 b, and a spacer 304 c, and agate protection layer 304 d. The material of the gate dielectric layer304 a, for example, is silicon oxide. The material of the gate 304 b,for example, is doped polysilicon, the material of the spacer 304 c, forexample, is silicon oxide, and the material of the gate protection layer304 d, for example, is silicon nitride or silicon oxide. Furthermore,the substrate 300 below the gate structure 304 is the channel region 306of the metal oxide semiconductor field effect transistor.

Later, referring to FIG. 3B, a dry etching process 308 is performed, anda portion of the substrate 300 is removed at the two side walls of thegate structure in the substrate 300 to form a recess 310. The dryetching process 308, for example, is reactive ion etching.

Later, referring to FIG. 3C, a source/drain extension layer 312 isformed inside the recess 310. The material of the source/drain extensionlayer 312 for example, is silicon carbide. The composite structure ofthe silicon carbide is typically represented by SiXC_(1-x), or directlyrepresented by SiC. In which, the range for X is from 0 to 1.Furthermore, the structure of the source/drain extension layer 312, forexample, is epitaxy. The method of fabrication of the source/drainextension layer 312, for example, is selective epitaxial deposition,which allows silicon carbide to only grow on the silicon, and not on thesilicon oxide or the silicon nitride. In other words, silicon carbideonly grows on the recess 310, and not on the spacer 304, the gateprotection layer 304 d, and the isolation structure 302. The selectiveepitaxial deposition, for example, is vapor-phase epitaxial fabrication,which includes low-pressure chemical vapor deposition epitaxial growth,atmospheric pressure CVD epitaxial growth, and ultra-high vacuum CVDepitaxial growth.

One thing worthy of mentioning is that, the lattice constant of carbonis less than silicon, therefore, the source/drain extension layer 312which adopts silicon carbide as material is a strained layer. In otherwords, the silicon carbide lattice of the source/drain extension layer312, due to stretching stress, produces an anisotropic structure,thereby changing the conduction band and the valence band. When thesource/drain extension layer 312 and the substrate 300 are integrated,the conduction band and the valence band can be tailored to performdesign discontinuously to produce quantum well and built-in electricfield, therefore, the rate of penetration of the carrier of theinterface between the source/drain extension layer 312 and the substrate300 is allowed to be increased. In summary, the source/drain extensionlayer 312, by adopting silicon carbide as material, can improve theefficiency of the metal oxide semiconductor field effect transistor.

Furthermore, the source/drain extension layer 312, for example, includesN-type dopants. N-type dopants, for example, are intended to performin-situ doping injection during the forming of the source/drainextension layer 312. In comparison with ex-situ, in-situ doping allowsthe source/drain extension layer 312 to have higher activation dopingconcentration. The higher activation doping concentration increases thesaturation-region drain current and the linear-region drain current ofthe transistor. Of course, N-type dopants can also perform ex-situdoping injection after the forming the source/drain extension layer 312.Furthermore, N-type dopants, for example, are boron ions or arsenicions. One thing worthy of mentioning is that, after the forming of thesource/drain extension layer 312, the procedure for doping activationannealing will typically be performed, thus allowing the diffusion ofN-type dopant towards the channel region 306 below the gate structure304. For the effective controlling of the diffusion rate of the N-typedopants, in the present embodiment, prior to the forming of thesource/drain extension layer 312, a dopant diffusion barrier layer 314formed inside the recess 310 is further included, but the presentinvention is not limited to this. The material of the dopant diffusionbarrier layer 314, for example, is silicon carbide. Furthermore, thedopant diffusion barrier layer 314, for example, includes P-typedopants, for preventing excessive amount of N-type dopant from diffusingtowards the channel region 306. The method of fabrication of the dopantdiffusion barrier layer 314, for example, is the aforementionedselective epitaxial deposition. Furthermore, in another embodiment, thecarbon composition ratio of the portion of the source/drain extensionlayer 312 adjacent to the substrate 300, for example, is larger than thecarbon composition ratio of the portion of the source/drain extensionlayer 312 at a farther distance to the substrate 300. This type ofdesign allows a portion of the source/drain extension layer 312 adjacentto the channel region 306 to have more carbon atoms, to block excessiveamount of N-type dopant to diffuse towards the channel region 306.Furthermore, the carbon composition ratio of the source/drain extensionlayer 312, for example, is of gradient distribution. Thus it can be seenthat, when the source/drain extension layer 312 includes N-type dopant,it is possible to utilize the carbon distribution of the source/drainextension layer 312 to control the amount of N-type dopant which isdiffused towards the channel region 306.

Later, referring to FIG. 3D, a spacer 316 is formed on the two sidewalls of the gate structure 304. The material of the spacer 316, forexample, is silicon nitride, and the method of fabrication of the spacer316 in the present invention is of a conventional technique used andknown by those skilled in the art, therefore, no further details arerequired.

Later, referring to FIG. 3E, a layer of dielectric layer 318 is formedon the isolation structure 302. The material of the dielectric layer318, for example, is silicon oxide or silicon nitride. The method offabrication of the dielectric layer 318, for example, is to first form alayer of the dielectric layer over all of the structures illustrated inFIG. 3D, then to perform photolithography and etching to expose thespacer 316 and the source/drain extension layer 312, and then to formingit. Later, using the spacer 316 and the dielectric layer 318 as a mask,a dry etching process 320 is performed for removing a portion of thesource/drain extension layer 312 and a portion of the substrate 300 toform a recess 322. Furthermore, because the metal oxide semiconductorfield effect transistor of the present embodiment further includes thedopant diffusion barrier layer 314, therefore, the dry etching process320 further includes the removal of a portion of the dopant diffusionbarrier layer 314. In addition, the reaction gas used in the dry etchingprocess 320 during removal of silicon carbide is, for example, CF₄,C₄F₈, or C₅F₁₀.

Later, referring to FIG. 3F, a source/drain layer 324 is depositedinside the recess 322. The material of the source/drain layer 324, forexample, is silicon carbide, The structure of the source/drain layer324, for example, is epitaxy. In addition, because the material of thesource/drain layer 324 is silicon carbide, therefore, the source/drainlayer 324 is a strained layer, thus the efficiency of the metal oxidesemiconductor field effect transistor can be improved. The method offabrication of the source/drain layer 324, for example, is theaforementioned selective epitaxial deposition, to allow silicon carbidegrow only on the silicon, and not grow on silicon oxide or siliconnitride. In other words, silicon carbide will only grow on the recess322, and will not grow on the gate protection layer 304 d, the spacer316 and the dielectric layer 318. Furthermore, the source/drain layer324, for example, includes N-type dopant. N-type dopants, for example,during the forming of the source/drain layer 324, are intended toperform in-situ doping injection. In comparison with ex-situ doping,in-situ doping can make the source/drain layer 324 to have higheractivation doping concentration. The high activation dopingconcentration will increase the saturation-region drain current and thelinear-region drain current of the transistor. Of course, ex-situ dopinginjection can be performed after the forming of the source/drain layer324. Furthermore, N-type dopant of the source/drain layer 324, forexample, is phosphorous ion or arsenic ion.

Later, referring to FIG. 3G, the dielectric layer 318 and the gateprotection layer 304 d is removed. The method for removal of the gateprotection layer 304 d and the dielectric layer 318, for example, is awet etching process, and this wet etching process, for example, is usinghot phosphoric acid or hydrofluoric acid as an etchant. Later, a metalsilicide layer 326 is formed on the gate 304 b, on the gate structure302 and also on the source/drain layer 324, for decreasing the contactresistance between the subsequently formed contact and the source/drainlayer 324, and the contact resistance between the contact and the gate304 b. The material of the silicide layer 326, for example, is nickelsilicide or other metal silicides. The method of fabrication of themetal silicide layer 326, for example, is to first deposit a layer ofnickel, and then to perform a rapid thermal anneal. The material andmethod of fabrication of the aforementioned metal silicide layer 326 isexemplary, however, the present invention is not limited to this only.Later, subsequent procedures are performed for the completion of thefabrication of the metal oxide semiconductor field effect transistor.

Because a layer of dopant diffusion barrier layer is first formed priorto forming of the source/drain extension layer in the present invention,therefore, the N-type dopants are blocked because of activationannealing is then diffused towards the channel region after forming ofthe source/drain extension layer. Furthermore, because the carboncomposition ratio of the portion of the source/drain extension layeradjacent to the substrate, for example, is larger than the carboncomposition ratio of the portion of the source/drain extension layer ata farther distance to the substrate, therefore, N-type dopant, becauseof activation annealing, can have controlled rate of diffusion towardsthe channel region. Because the diffusion rate of the N-type dopantstowards the channel region is well controlled, therefore, fabricationtolerance is increased.

Fourth Embodiment

FIG. 4 is a cross-sectional view of a metal oxide semiconductor fieldeffect transistor, according to another embodiment of the presentinvention.

Referring to FIG. 4, the metal oxide semiconductor field effecttransistor mainly includes a substrate 400, an isolation structure 402,a gate structure 404, a spacer 416, a source/drain extension layer 412,and a source/drain layer 424. The substrate 400, for example, is asilicon-based substrate, a silicon on insulator (SOI) substrate, agermanium channel substrate, a substrate having bulk strain, and asubstrate having crystallographic orientation. The gate structure 404 isdisposed on the substrate 400 between the isolation structures 402. Aportion of the substrate below the gate structure 404 is the channelregion 406 of the metal oxide semiconductor field effect transistor. Thespacer 416 is disposed on the side wall of the gate structure 404. Thesource/drain extension layer 412 is disposed in the substrate 400 belowthe spacer 416, and the source/drain layer 424 is disposed in thesubstrate 400 outside of the spacer 416, and the depth of thesource/drain layer 424 is larger than the depth of the source/drainextension layer 412. The source/drain extension layer 412 and thesource/drain layer 424 are both strained layers. The following are thedetailed description of the advantages and structure of the two strainedlayers:

The structure of the source/drain extension layer 412, for example, isepitaxy, and the structure of the source/drain layer 424 can also beepitaxy. Furthermore, the material of the source/drain extension layer412, for example, is silicon carbide, and the material of thesource/drain layer 424 can also be silicon carbide. Because the carbonlattice is lesser than silicon, therefore, the source/drain extensionlayer 412 and the source/drain layer 424, which adopt silicon carbide asmaterial, are strained layers. The source/drain extension layer 412 andthe source/drain layer 424 will apply a tensile stress towards thechannel region 406. Furthermore, the source/drain extension layer 412adopting silicon carbide as material can allow the rate of penetrationof the carrier of the interface between the source/drain extension layer412 and the substrate 400 to be increased, thus improving the efficiencyof the metal oxide semiconductor field effect transistor.

Furthermore, the source/drain extension layer 412, for example, includesN-type dopants. The N-type dopants, for example, are phosphorous ions orarsenic ions. The carbon composition ratio of the portion of thesource/drain extension layer 412 adjacent to the substrate 400, forexample, is larger than the carbon composition ratio of the portion ofthe source/drain extension layer 412 at a farther distance to thesubstrate 400, as a result, the N-type dopants of the source/drainextension layer 412, is prevented from diffusing towards the channelregion 406 because of heat, or at least the quantity of N-type dopantsdiffused towards the channel region 406 is controlled. Furthermore, thecarbon composition ratio of the source/drain extension layer 412, forexample, is of gradient distribution. Furthermore, the metal oxidesemiconductor field effect transistor of the present invention furtherincludes a layer of dopant diffusion barrier layer 414, disposed betweenthe source/drain extension layer 412 and the substrate 400. The materialof the dopant diffusion barrier layer 414, for example, is siliconcarbide, and the dopant diffusion barrier layer 414, for example,includes P-type dopant. Because of the set up of the dopant diffusionbarrier layer 414, therefore, the N-type dopants, because of heating, isthus diffused towards the channel region 406 and can be further blockedor controlled, or at least the quantity of the N-type dopant diffusedtowards the channel region 406 can be controlled. In addition, thesource/drain layer 424 can also include N-type dopant, and the N-typedopants, for example, are phosphorous ions or arsenic ions.

Because the source/drain extension layer and the source/drain layer ofthe metal oxide semiconductor field effect transistor of the presentinvention are both strained layers and the material of the source/drainextension layer and of the source/drain layer are both silicongermanium, therefore, the efficiency of the metal oxide semiconductorfield effect transistor can be increased. In addition, because of theset up of the dopant diffusion barrier layer and the source/drainextension layer having a specific distribution method for carboncomposition ratio, therefore, the dopant inside of the source/drainextension layer which are diffused towards the channel region due toheating can be blocked, or at least the quantity of the dopants whichare diffused towards the channel region can be controlled.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing descriptions, it is intended that the presentinvention covers modifications and variations of this invention if theyfall within the scope of the following claims and their equivalents.

1. A metal oxide semiconductor field effect transistor, comprising: asubstrate; a gate structure, disposed on the substrate; a spacer,disposed on a side wall of the gate structure; a source/drain extensionlayer, disposed in the substrate and below the spacer; a source/drainlayer, disposed in the substrate and outside of the spacer, wherein thedepth of the source/drain layer is larger than the depth of thesource/drain extension layer; and a dopant diffusion barrier layer,disposed directly under the source/drain extension layer and in a sideof the source/drain extension layer near the gate structure; wherein anentire of the source/drain layer is comprised of a strained materialcomprising two different atoms.
 2. The metal oxide semiconductor fieldeffect transistor of claim 1, wherein the strained material is silicongermanium.
 3. The metal oxide semiconductor field effect transistor ofclaim 1, wherein the source/drain extension layer is comprised of thestrained material.
 4. The metal oxide semiconductor field effecttransistor of claim 3, wherein the dopant diffusion barrier layer iscomprised of the strained material.
 5. The metal oxide semiconductorfield effect transistor of claim 1, wherein the strained material issilicon carbide.
 6. A metal oxide semiconductor field effect transistor,comprising: a substrate; a gate structure, disposed on the substrate; aspacer, disposed on a side wall of the gate structure; a source/drainextension layer, disposed in the substrate and below the spacer; asource/drain layer, disposed in the substrate and outside of the spacer,wherein the depth of the source/drain layer is larger than the depth ofthe source/drain extension layer; and a dopant diffusion barrier layer,disposed directly under the source/drain extension layer; wherein anentire of the source/drain extension layer and the dopant diffusionbarrier layer are comprised of a strained material comprising twodifferent atoms.
 7. The metal oxide semiconductor field effecttransistor of claim 6, wherein the source/drain extension layer and thedopant diffusion barrier layer are located between an edge of the gatestructure and an edge of the source/drain layer.
 8. The metal oxidesemiconductor field effect transistor of claim 6, wherein the dopantdiffusion barrier layer is further disposed directly in a side of thesource/drain extension layer near the gate structure.
 9. The metal oxidesemiconductor field effect transistor of claim 8, wherein a gap isdisposed between the source/drain extension layer, the dopant diffusionbarrier layer and the edge of the gate structure.
 10. The metal oxidesemiconductor field effect transistor of claim 6, wherein thesource/drain extension layer and the dopant diffusion barrier layer areof different conductivity types.
 11. A metal oxide semiconductor fieldeffect transistor, comprising: a substrate; a gate structure, disposedon the substrate; a spacer, disposed on a side wall of the gatestructure; a source/drain extension layer, disposed in the substrate andbelow the spacer; a source/drain layer, disposed in the substrate andoutside of the spacer, wherein the depth of the source /drain layer islarger than the depth of the source/drain extension layer; and a dopantdiffusion barrier layer, disposed directly under the source/drainextension layer; wherein a top surface of the source/drain extensionlayer is higher than a top surface of the substrate.
 12. The metal oxidesemiconductor field effect transistor of claim 11, wherein a top surfaceof the source/drain layer is higher than the top surface of thesource/drain extension layer.
 13. The metal oxide semiconductor fieldeffect transistor of claim 11, wherein an entire of the source/drainextension layer is comprised of a strained material comprising twodifferent atoms.
 14. The metal oxide semiconductor field effecttransistor of claim 11, wherein the strained material is silicongermanium.
 15. The metal oxide semiconductor field effect transistor ofclaim 14, wherein the germanium composition ratio of the source/drainextension layer is of gradient distribution.
 16. The metal oxidesemiconductor field effect transistor of claim 15, wherein the germaniumcomposition ratio of the portion of the source/drain extension layeradjacent to the substrate is larger than the germanium composition ratioof the portion of the source/drain extension layer disposed at a fartherdistance to the substrate.